Cache memory

Results: 1188



#Item
821Microprocessors / Central processing unit / Parallel computing / Instruction set architectures / Computer memory / TILE64 / CPU cache / TILE-Gx / Thread / Computer architecture / Computer hardware / Computing

64bit SMP NetBSD OS Porting for TILE-Gx VLIW Many-Core Processor Toru Nishimura Sanctum Networks, Pvt. Ltd. [removed]

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Source URL: 2013.asiabsdcon.org

Language: English - Date: 2014-01-03 03:46:16
822Computer memory / Database management systems / Virtual memory / Cache / Relational database management systems / Page cache / Page table / Extensible Storage Engine / Lookup table / Computing / Information science / Information

No Bits Left Behind Eugene Wu Carlo Curino MIT CSAIL

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Source URL: db.csail.mit.edu

Language: English - Date: 2011-02-19 16:11:15
823Computing / Data / Transactional memory / Software transactional memory / Linearizability / Snapshot / Cache / Rock / Transaction processing / Concurrency control / Data management

Hardware Support for Unbounded Transactional Memory by Sean Lie

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Source URL: supertech.csail.mit.edu

Language: English - Date: 2014-09-16 08:27:50
824Computer memory / Central processing unit / Concurrency control / Instruction set architectures / CPU cache / Memory barrier / Parallel computing / Linearizability / Cache / Computer architecture / Computing / Computer hardware

Location-Based Memory Fences Edya Ladan-Mozes I-Ting Angelina Lee Dmitry Vyukov∗

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Source URL: supertech.csail.mit.edu

Language: English - Date: 2014-09-16 08:27:50
825Computational complexity theory / Analysis of algorithms / Concurrent computing / Parallel computing / Cache / Scheduling / Algorithm / Thread / Cilk / Theoretical computer science / Computing / Applied mathematics

An Analysis of Dag-Consistent Distributed Shared-Memory Algorithms Robert D. Blumofe Matteo Frigo† Christopher F. Joerg† Charles E. Leiserson† Keith H. Randall†  

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Source URL: supertech.csail.mit.edu

Language: English - Date: 2014-09-16 08:27:51
826Central processing unit / Threads / Microprocessors / Parallel computing / Computer memory / CPU cache / Multithreading / Computing / Computer hardware / Computer architecture

code::dive code::dive conference 5th of November 2014

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Source URL: araw.pl

Language: English - Date: 2014-09-02 12:10:01
827Computer science / Computing / Virtual memory / Cache / Page replacement algorithm / Cache-oblivious algorithm / Paging / Competitive analysis / Adversary model / Analysis of algorithms / Online algorithms / Computer memory

The Worst Page-Replacement Policy Kunal Agrawal1 , Michael A. Bender2 , and Jeremy T. Fineman1 1 2

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Source URL: supertech.csail.mit.edu

Language: English - Date: 2014-09-16 08:27:49
828Data / Information / Computer memory / Programming language implementation / Software transactional memory / Transactional memory / CPU cache / Linearizability / Extensible Storage Engine / Transaction processing / Concurrency control / Data management

Unbounded Transactional Memory C. Scott Ananian Krste Asanovi´c Bradley C. Kuszmaul Charles E. Leiserson Sean Lie MIT Computer Science and Artificial Intelligence Laboratory The Stata Center, 32 Vassar St., Cambridge, M

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Source URL: supertech.csail.mit.edu

Language: English - Date: 2014-09-16 08:27:52
829Parallel computing / Cilk / Thread / CPU cache / Charles E. Leiserson / Speedup / Shared memory / Linearizability / Intel Cilk Plus / Computing / Concurrent computing / Computer programming

Dag-Consistent Distributed Shared Memory Robert D. Blumofe Matteo Frigo Christopher F. Joerg Charles E. Leiserson Keith H. Randall MIT Laboratory for Computer Science 545 Technology Square Cambridge, MA 02139

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Source URL: supertech.csail.mit.edu

Language: English - Date: 2014-09-16 08:27:50
830Data / Information / Database management systems / Databases / Software transactional memory / Transactional memory / Serializability / Multiversion concurrency control / Database transaction / Transaction processing / Data management / Concurrency control

Concurrent Cache-Oblivious B-Trees Using Transactional Memory Bradley C. Kuszmaul ABSTRACT Cache-oblivious B-trees for data sets stored in external memory represent an application that can benefit from the use of transac

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Source URL: supertech.csail.mit.edu

Language: English - Date: 2014-09-16 08:27:49
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